How well has Moore's Law held up?
On this page
Moore’s Law is the best-known entry in my laws note. It is also the one people most often call dead. So I gathered twenty CPUs, checked each transistor count against a primary or reputable source, and put Moore’s forecast next to them.
What Moore said
In April 1965 Gordon Moore wrote “Cramming more components onto integrated circuits” for Electronics. He predicted that the number of components on a chip would double every year for the next ten years. At the 1975 IEEE International Electron Devices Meeting he slowed that to every two years (Computer History Museum). The two-year version is the one we still quote.
The chart
Each dot is a CPU, from the Intel 4004 (1971, 2,300 transistors) to AMD’s EPYC Turin (2024, about 150 billion). The y-axis is logarithmic, so steady doubling draws a straight line. The orange line starts at the 4004 and doubles every N years; drag the slider to change N. Pick an era to see what let chipmakers keep adding transistors in that period.
Best fit across all 20 chips: a doubling every 2.09 years. Your 2.0-year line doubles faster than real chips did, so it overshoots them. By 2025 it predicts 309B transistors; the largest chip here has 150B.
Eras — pick one to read what drove it:
Sources and data
| Chip | Year | Transistors | Source |
|---|---|---|---|
| Intel 4004 | 1971 | 2,300 | Intel, Microprocessor Quick Reference Guide Wikipedia's table lists 2,250; Intel and the Computer History Museum both give 2,300. |
| Intel 8008 | 1972 | 3,500 | Intel, Microprocessor Quick Reference Guide |
| Intel 8086 | 1978 | 29,000 | Intel, Microprocessor Quick Reference Guide |
| Intel 80286 | 1982 | 134,000 | Intel, Microprocessor Quick Reference Guide |
| Intel 386 DX | 1985 | 275,000 | Intel, Microprocessor Quick Reference Guide Intel's guide dates it October 1985; the 1993 IEEE Micro paper lists 1986. |
| Intel 486 DX | 1989 | 1,200,000 | Intel, Microprocessor Quick Reference Guide |
| Intel Pentium | 1993 | 3,100,000 | Alpert & Avnon (Intel), “Architecture of the Pentium Microprocessor”, IEEE Micro, 1993 |
| Intel Pentium Pro | 1995 | 5,500,000 | Intel, Microprocessor Quick Reference Guide |
| Intel Pentium 4 (Willamette) | 2000 | 42,000,000 | Intel, Microprocessor Quick Reference Guide |
| IBM POWER4 | 2001 | 174,000,000 | IBM Journal of Research and Development, “The circuit and physical design of the POWER4 microprocessor”, 2002 |
| Intel Core 2 Duo (Conroe) | 2006 | 291,000,000 | Intel, Microprocessor Quick Reference Guide |
| Intel Itanium 2 dual-core (Montecito) | 2006 | 1,720,000,000 | Intel, Microprocessor Quick Reference Guide |
| Intel Xeon 7500 (Nehalem-EX) | 2010 | 2,300,000,000 | Intel press release, “Intel Previews Intel Xeon ‘Nehalem-EX’ Processor”, 2009 Previewed in 2009; launched 30 March 2010. |
| IBM POWER8 | 2014 | 4,200,000,000 | Fluhr et al. (IBM), “POWER8: A 12-core server-class processor in 22nm SOI”, ISSCC 2014 |
| Oracle SPARC M7 | 2015 | 10,000,000,000 | SiliconANGLE, “Oracle debuts first systems with 10-billion-transistor SPARC M7 chip”, 2015 Oracle gave the count as “over 10 billion” when it showed the chip at Hot Chips 2014. |
| AMD EPYC Rome (64-core) | 2019 | 39,540,000,000 | HEXUS, “AMD Epyc Rome CPU put under the microscope”, 2020 Nine dies: one 8.34B I/O die plus eight 3.9B core dies, as reported by Hardwareluxx. Other reports give 3.8B per core die, which would total about 38.7B. |
| IBM Power10 | 2021 | 18,000,000,000 | The Register, “IBM takes Power10 processors down to 7nm with Samsung”, 2020 Shown at Hot Chips in August 2020; shipped in 2021. |
| AMD EPYC Genoa (96-core) | 2022 | 90,000,000,000 | APH Networks, “AMD Unveils 4th Gen Epyc ‘Genoa’ Server Chips”, 2022 Press reports give “up to 90 billion”; AMD's launch press release gives no count. |
| AMD EPYC Turin (128-core) | 2024 | 150,000,000,000 | Wccftech, “AMD 5th Gen EPYC Turin CPUs Launched”, 2024 From AMD's launch slides as reported by Wccftech; up to 17 chiplets. No AMD page with this figure was found. |
| IBM Telum II | 2025 | 43,000,000,000 | IBM Research, “IBM Telum II: Next Generation 5.5GHz Microprocessor”, ISSCC 2025 A single 600 mm² die, unlike the multi-die EPYC chips. |
Events
- 1965: “Cramming more components onto integrated circuits” (Electronics, 19 April 1965) predicted that components per chip would double every year. Computer History Museum, “1965: Moore's Law predicts the future of integrated circuits”
- 1975: At the 1975 IEEE International Electron Devices Meeting, Moore slowed his forecast to a doubling every two years. Computer History Museum, “1965: Moore's Law predicts the future of integrated circuits”
- 2005: Leakage made it hard to keep lowering voltage with each shrink, so faster clocks meant more heat. In 2004 Intel cancelled its next single-core Pentium 4 for power reasons and moved to dual-core designs due in 2005; AMD also had dual-core chips coming in 2005. Bohr (Intel), “A 30 Year Retrospective on Dennard's MOSFET Scaling Paper”, IEEE SSCS News, 2007 · EE Times, “Intel cancels Tejas, moves to dual-core designs”, 2004 · Sutter, “The Free Lunch Is Over”, Dr. Dobb's Journal, 2005
What the best fit says
A least-squares fit through all twenty chips gives a doubling about every 2.1 years. Moore’s 1975 forecast was close to right for half a century. Set the slider to 2.0 and the line tracks the dots closely from the 4004 to the mid-2000s.
The fit hides a bend, though. Fitting only the chips before 2005 gives almost exactly 2.0 years. Fitting only the chips from 2005 on gives about 2.7 years. With ten chips from four makers, that second number is rough, but every chip since 2020 sits below the 2-year line.
Where the trend bent
Moore’s Law counts transistors. For thirty years it came with a bonus: Dennard scaling. Shrink a transistor and it switches faster and uses less power, so power per square millimetre stays flat. Mark Bohr of Intel describes how that broke. By the 65 nm generation the gate oxide was about five atoms thick, and leakage made it hard to lower voltage any further.
Without lower voltage, faster clocks meant more heat. Herb Sutter pointed out in 2005 that clock speeds had flattened around 2003 while transistor counts kept climbing (The Free Lunch Is Over). In 2004 Intel cancelled Tejas, its next single-core Pentium 4, and moved to dual-core designs (EE Times). Sutter predicted that from then on, extra transistors would go into more cores and more cache rather than higher clock speeds.
Cost bent too. Cheaper transistors used to come free with each shrink. In 2014 Zvi Or-Bach of MonolithIC 3D argued that cost per transistor stopped falling at 28 nm. Milind Shah of Google backed the claim at IEDM 2023 (Semiconductor Digest).
The biggest recent dots also count something new: packages, not dies. EPYC Rome’s 39.5 billion transistors sit on nine dies (HEXUS). IBM’s Telum II is a single 600 mm² die and holds 43 billion (IBM Research). Part of the recent growth comes from putting more dies in one package, not from denser dies alone.
So, has it held up?
As a statement about transistor counts, mostly yes. The best fit over fifty years is within about a month of Moore’s 1975 forecast. As a promise of faster, cooler and cheaper chips every two years, no. That promise ended in the mid-2000s. What survives is a count that keeps doubling, now through new transistor shapes, extreme-ultraviolet lithography and many dies in one package, at a slower pace and a higher price.
A note on the data: I list only CPUs, not GPUs or AI accelerators, and I date each chip by the year it shipped. Every value, with its source and any disagreement between sources, is in the “Sources and data” table under the chart.